本书是“国外电子与通信教材系列”之一，全书共分13个章节，主要介绍了如何使用Cadence和Synopsys公司的CAD工具来实际设计数字VLSI芯片，具体内容包括电路图输入、Verilog仿真、版图编辑、标准单元设计、模拟和数模混合信号仿真、单元表征和建库等。该书可供各大专院校作为教材使用，也可供从事相关工作的人员作为参考用书使用。

本书介绍如何使用Cadence和Synopsys公司的CAD工具来实际设计数字VLSI芯片。读者通过本书可以循序渐进地学习这些CAD工具，并使用这些软件设计出可制造的数字集成电路芯片。本书内容按集成电路的设计流程编排，包括CAD设计平台、电路图输入、Verilog仿真、版图编辑、标准单元设计、模拟和数模混合信号仿真、单元表征和建库、Verilog综合、抽象形式生成、布局布线及芯片总成等工具；每一工具的使用都以实例说明，最后给出了一个设计简化MIPS微处理器的完整例子。本书可与有关集成电路设计理论的教科书配套使用，可作为高等院校有关集成电路设计理论类课程的配套教材和集成电路设计实践类课程的教科书，也可作为集成电路设计人员的培训教材和使用手册。

1 Introduction

 1.1 CAD Tool Flows

1.1.1 Custom VLSI and Cell Design Flow

1.1.2 Hierarchical Cell/Block ASIC Flow

 1.2 What This Book Is and Isn't

 1.3 Bugs in the Tools?

 1.4 Tool Setup and Execution Scripts

 1.5 Typographical Conventions

2 Cadence DFII and ICFB

 2.1 Cadence Design Framework

 2.2 Starting Cadence

 2.3 Summary

3 Composer Schematic Capture

 3.1 Starting Cadence and Making a New

Working Library

 3.2 Creating a New Cell

3.2.1 Creating the Schematic View of a Full Adder

3.2.2 Creating the Symbol View of a Full Adder

3.2.3 Creating a Two-Bit Adder Using the FullAdder Bit

 3.3 Schematics that Use Transistors

 3.4 Printing Schematics

3.4.1 Modifying PostScript Plot Files

 3.5 Variable, Pin, and Cell Naming Restrictions

 3.6 Summary

4 Verilog Simulation

 4.1 Verflog Simulation of Composer Schematics

4.1.1 Verilog-XL: Simulating a Schematic

4.1.2 NC_Verilog: Simulating a Schematic

4.2 Behavioral Verilog Code in Composer

4.2.1 Generating a Behavioral View

4.2.2 Simulating a Behavioral View

 4.3 Stand-Alone Verilog Simulation

4.3.1 Verilog-XL

4.3.2 NC_Verilog

4.3.3 VCS

 4.4 Timing in Verilog Simulations

4.4.1 Behavioral Versus Transistor Switch Simulation

4.4.2 Behavioral Gate Timing

4.4.3 Standard Delay Format (SDF) Timing

4.4.4 Transistor Timing

 4.5 Summary

5 Virtuoso Layout Editor

 5.1 An Inverter Schematic

5.1.1 Starting Cadence kfb

5.1.2 Making an Inverter Schematic

5.1.3 Making an Inverter Symbol

 5.2 Layout for an Inverter

5.2.1 Creating a New layout View

5.2.2 Drawing an nmosTransistor

5.2.3 Drawing a pmos Transistor

5.2.4 Assembling the Inverter from the Transistor Layouts

5.2.5 Using Hierarchy in Layout

5.2.6 Virtuoso Command Overview

……

6 Standard Cell Design Template

7 Spectre Analog Simulator

8 Cell Characterization

9 Verilog Synthesis

10 Abstract Generation

11 SOC Encounter Place and Route

12 Chip Assembly

13 Design Example

A Tool and Setup Scripts

B Scripts to Drive the Tools

C Technology and Cell Libraries

Bibliography

Index