本书是作者多年来在得克萨斯大学奥斯汀分校讲授数字系统设计课程的经验积累。书中总结了VHDL语言的常规和高级文法特点，介绍了数字系统中运算部件从简单到复杂的设计方法，基于SM图实现复杂控制逻辑的VHDL设计方法，以及运算部件和控制逻辑的系统整合方法。书中提供了大量的设计实例可供参考，适用于本科高年级同学和研究生对数字系统进行VHDL设计与实现。

本书对原著进行了结构调整，使之更适合作为本科双语教学教材。第1章首先回顾了逻辑设计基本原理，第2章和第3章分别讲解了VHDL基本知识和高级主题，第4章为简单设计实例，第5章讨论状态机，第6章讨论浮点数运算，第7章讨论硬件测试和可测试性设计，第8章给出了一些高级设计实例。全书将工业标准硬件描述语言VHDL和数字系统设计融为一体，较好地实现了控制逻辑和运算部件的整合设计，并给出了多个设计实例，便于学生在实践中得到提高。

本书适合作为高等院校电子、电气和计算机专业本科生数字系统设计类课程的双语教学教材，也适合作为相关工程技术人员的参考书。

Chapter 1 Review of Logic Design Fundamentals

 1.1 Combinational Logic

 1.2 Boolean Algebra and Algebraic Simplification

 1.3 Karnaugh Maps

 1.4 Designing with NAND and NOR Gates

 1.5 Hazards in Combinational Circuits

 1.6 Flip-Flops and Latches

 1.7 Mealy Sequential Circuit Design

 1.8 Moore Sequential Circuit Design

 1.9 Equivalent States and Reduction of State Tables

 1.10 Sequential Circuit Timing

 1.11 Tristate Logic and Busses

 1.12 Problems

Chapter 2 Introduction to VHDL

 2.1 Computer-Aided Design

 2.2 Hardware Description Languages

 2.3 VHDL Description of Combinational Circuits

 2.4 VHDL Modules

 2.5 Sequential Statements andVHDL Processes

 2.6 Modeling Flip-Flops Using VHDL Processes

 2.7 Processes Using Wait Statements

 2.8 Two Types of VHDL Delays: Transport and Inertial Delays

 2.9 Compilation, Simulation, and Synthesis of VHDL Code

 2.10 VHDL Data Types and Operators

 2.11 Simple Synthesis Examples

 2.12 VHDL Models for Multiplexers

 2.13 VHDL Libraries

 2.14 Modeling Registers and Counters Using VHDL Processes

 2.15 Behavioral and Structural VHDL

 2.16 Variables, Signals, and Constants

 2.17 Arrays

 2.18 Loops in VHDL

 2.19 Assert and Report Statements

 2.20 Problems

Chapter 3 Additional Topics in VHDL

 3.1 VHDL Functions

 3.2 VHDL Procedures

 3.3 Attributes

 3.4 Creating Overloaded Operators

 3.5 Multi-Valued Logic and Signal Resolution

 3.6 The IEEE 9-Valued Logic System

 3.7 SRAM Model Using IEEE 1164

 3.8 Model for SRAM Read/Write System

 3.9 Generics

 3.10 Named Association

 3.11 Generate Statements

 3.12 Files and TEXTIO

 3.13 Problems

Chapter 4 Design Examples

 4.1 BCD to Seven-Segment Display Decoder

 4.2 A BCD Adder

 4.3 32-Bit Adders

 4.4 Traffic Light Controller

 4.5 State Graphs for Control Circuits

 4.6 Scoreboard and Controller

 4.7 Synchronization and Debouncing

 4.8 A Add-and-Shift Multiplier

 4.9 Array Multiplier

 4.10 A Signed Integer/Fraction Muliplier

 4.11 Keypad Scanner

 4.12 Binary Dividers

 4.13 Problems

Chapter 5 SM Charts and Microprogramming

 5.1 State Machine Charts

 5.2 Derivation of SM Charts

 5.3 Realization of SM Charts

 5.4 Implementation of the Dice Game

 5.5 Problems

Chapter 6 Floating-Point Arithmetic

 6.1 Representation of Floating-Point Numbers

 6.2 Floating-Point Multiplication

 6.3 Floating-Point Addition

 6.4 Other Floating-Point Operations

 6.5 Problems

Chapter 7 Hardware Testing and Design for Testability

 7.1 Testing Combinational Logic

 7.2 Testing Sequential Logic

 7.3 Scan Testing

 7.4 Boundary Scan

 7.5 Built-In Self-Test

 7.6 Problems

Chapter 8 Additional Design Examples

 8.1 Design of a Wristwatch

 8.2 Memory Timing Models

 8.3 A Universal Asynchronous Receiver Transmitter

 8.4 Problems

Appendix A

VHDL Language Summary

Appendix B

IEEE Standard Libraries

Appendix C

TEXTIO Package

Appendix D

Projects

References